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Type: Improvement
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Resolution: Duplicate
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Priority: Major - P3
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None
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Affects Version/s: None
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Component/s: None
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2023-05-02 StorEng Bug Bash
Summary
On x86, reads from memory are not reordered with other reads, which makes the LFENCE instruction unnecessary. We should consider removing it from WT_READ_BARRIER and turning it just into a compiler barrier, confirm that it is indeed safe, and evaluate any potential performance improvement.
Acceptance Criteria
The solution should remove LFENCE from WT_READ_BARRIER on x86, provide a solid argument for why it is safe, and at least roughly quantify any performance improvement. However, if there is no performance improvement, or if removing LFENCE is not safe, it should be explained in the comments.
Note
If we proceed with changing our code to use C11 atomics per PM-3220, this ticket may not be relevant, as that should also not have an effect of eliminating the use of LFENCE on x86.
References
- Intel's Software Developers Manual, volume 3, section 8.2.2 (Memory Ordering in P6 and More Recent Processor Families)
- C/C++11 mappings to processors
- duplicates
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WT-10957 Evaluate not emitting lfence and sfence instructions on x86 for R/W barriers
- Closed